Job Description Fresh Electronics Engineers after training will be part of the team responsible for enhancing the world's largest portfolio of Verification IPs. You will work from specs and take the design through HDL coding, testing and release to customers.
Desired Candidate Profile Students from DCE/NSIT/NIT only Excellent academic track record (min 75%) Sound Digital Design fundamentals & knowledge of microprocessors is essential Knowledge of Verilog, C/C++ and OO concepts is preferred
Company Profile nSys Verification Suite family is the world's largest portfolio of Verification IPs. Global leaders in Semiconductor, System Houses, Networking & Storage industries use our products to accelerate their ASIC/SoC designs. We have offices in Delhi & CA
Company Name:nSys Design Systems Pvt. Ltd.
Executive Name:Shilpa
Address: NSYS Design Systems B-09, 707 ITL Twin Tower Netaji Subhash Place Pitampura NEW DELHI,Delhi,India 110034
